The present invention relates to methods of forming semiconductor devices and, more specifically, to methods of forming a non-volatile memory device.
Non-volatile memory devices retain their stored data even when their power supplies are interrupted. NAND flash memory devices, which are a kind of non-volatile memory devices, are widely used as mass storage media due to their advantage in high integration density. In recent years, patterns become much finer as the design rule is scaled down to achieve high integration density. One approach to obtaining finer patterns is to develop higher-performance exposure apparatus. However, development and replacement of an exposure apparatus can require an enormous cost, and it is can be difficult to develop/obtain a sufficiently stable light source and exposure technology. As a result, some approaches to the fabrication of semiconductor memory devices have reached a limit on integration density.
FIG. 1 is a top plan view of a conventional NAND flash memory device.
As illustrated in FIG. 1, a plurality of active regions 1 are arranged on a semiconductor substrate in one direction. A ground select gate line 2a and a string select gate line 2b cross over the plurality of active regions 1. A plurality of cell gate lines 3, 3a, and 3b cross over the plurality of active regions 1 between the ground select gate line 2a and the string select gate line 2b. Among the cell gate lines 3, 3a, and 3b, a cell gate line 3a adjacent to the ground select gate line 2a is defined as a first outer cell gate line 3a, and a cell gate line 3b adjacent to the string select gate line 2b is defined as a second outer cell gate line 3a. 
It is desirable to have excellent punchthrough characteristics for a ground select transistor including the ground select gate line 2a and a string select transistor including the string select gate line 2b. Accordingly, linewidths of the ground select and string select gate lines 2a and 2b are larger than those of the cell gate lines 3, 3a, and 3b. Increase of spaces at opposite sides adjacent to the ground select and string select gate lines 2a and 2b may be required to define the ground select and string select gate lines 2a and 2b having a relatively larger linewidth by means of an exposure process. Thus, a distance 4 between the ground select gate line 2a and the first outer cell gate line 3a is larger than a distance 5 between a pair of adjacent cell gate lines 3 and 3a or 3b. Similarly, a distance between the string select gate line 2b and the second outer cell gate line 3b is larger than the distance 5.
Accordingly, different spacing distances are provided on opposite sides of the first outer cell gate line 3a and adjacent other lines, and different spacing distances are provided on opposite sides of the second outer cell gate line 3b and adjacent other lines. Consequently, a first outer cell transistor including the first outer cell gate line 3a and the second outer cell transistor including the second outer cell gate line 3b have different characteristics from a cell transistor including another cell gate line 3. Characteristics of cells in such a conventional NAND flash memory device will now be described below with reference to FIG. 2.
FIG. 2 is a graph illustrating characteristics of cells in a conventional NAND flash memory device. In the graph of FIG. 2, the x-axis represents an erase threshold voltage and the y-axis represents positions of a cell transistor disposed between a ground select transistor and a string select transistor. A reference numeral “7a” denotes an erase threshold voltage 7a of a first outer cell transistor including a first outer cell gate line 3a, and a reference numeral “7b” denotes an erase threshold voltage 7b of a second outer cell transistor including a second outer cell gate line 3b. 
Referring to FIGS. 1 and 2, erase threshold voltages 7a and 7b of first and second outer cell transistors depart from (are different than) the illustrated trend of erase threshold voltages of another cell transistor disposed therebetween. As a result, the erase/program operation for the first and second outer cell transistors may become slower/faster than that for the above another cell transistor. For these reasons, cell characteristic dispersion of a NAND flash memory device increases due to unexpected characteristics of the first and second outer cell transistors, and the reliability margin of the NAND flash memory device may be reduced.
Because the distance 4 is lengthened, it may be difficult to achieve a high integration density of the NAND flash memory device and the resulting chip size of the NAND flash memory device may be increased.